The present invention relates to phase-locked loop (PLL) circuits and, more particularly, to reducing frequency lock time in phase-locked loop (PLL) circuits.
Electronic circuits such as microprocessors, microcontroller units (MCUs), system-on-chips (SOCs), and application specific integrated circuits (ASICs) are widely used in portable devices including personal digital assistants (PDAs), cell phones, and other handheld devices. These devices use phase-locked loops (PLLs) that generate an oscillator signal based on an input reference signal. The oscillator signal has a phase and frequency that is directly proportional with the corresponding phase and frequency of the input reference signal. In communication systems, the oscillator signal is used for modulation and demodulation of a message signal. In electronic circuits, the oscillator signal is used as a clock signal for synchronous operation of internal circuitry.
FIG. 1 illustrates a schematic diagram of a conventional PLL 100. The PLL 100 includes a voltage-controlled oscillator (VCO) 102, a frequency divider 104, a phase-frequency detector (PFD) 106, a charge pump 108 and a low pass filter 110. The VCO 102 generates an oscillator signal based on a control voltage. The phase detector 106 is connected to the VCO 102 by way of the frequency divider 104 and compares the phase of the oscillator signal with that of an input reference signal to generate an error signal based on the detected phase difference. The frequency divider 104 provides a fraction of the oscillator signal to the phase detector 106. The charge pump 108 is connected to the phase detector 106 and the VCO 102. The charge pump 108 receives the error signal and generates a charge pump current. The low pass filter 110, which is connected between the charge pump circuit 108 and the VCO 102, receives the charge pump current and generates the control voltage (Vctrl), which is then provided to the VCO 102 that turn generates the oscillator signal.
The oscillator signal generated by the PLL 100 is provided as a clock signal to an electronic circuit (not shown). Electronic circuits are often required to operate on a low supply voltage and consume less battery power to increase the operating life, and hence are frequently switched from a RUN mode to a LOW POWER mode, during periods of inactivity. A wake-up circuitry is provided in the electronic circuit to switch the electronic circuit from the LOW POWER mode to the RUN mode. The PLL 100 is switched OFF when the electronic circuit enters the LOW POWER mode and is switched ON when the electronic circuit wakes up from the LOW POWER mode and enters the RUN mode. After switching ON, the PLL 100 takes a finite time to reach the locking frequency (referred to as frequency lock time). For low bandwidth PLLs, the frequency lock time is quite high (about 100 μs) and considerably increases the wake-up time (time taken by the electronic circuit to transition from the LOW POWER mode to the RUN mode) of the electronic circuit. A high wake-up time degrades the performance of the electronic circuit. Wake-up time becomes crucial when such electronic circuits are used in time-critical applications and must be kept as low as possible to reduce the chances of failure of the electronic circuit.
Therefore, it would be advantageous to have a PLL with a reduced frequency lock time. It would be further advantageous to have a PLL that can be used with an electronic circuit and that reduces the wake-up time of the electronic circuit and eliminates the above mentioned shortcomings of existing PLLs.